Roadmap

Where LazyVerilog is heading. Themes, not promises: there are no dates, and the order can change.

• Hardening: fuzzing and correctness checks for every LSP feature; document highlight and smart selection.
• Editor depth: semantic highlighting, class type hierarchy, lint quick-fixes.
• Clocks: lazyverilog-clk generates an SDC clock skeleton from RTL; hover shows a register's clock domain.
• AI agents: an MCP server exposing lazyverilog navigation and clock data.

Ideas and requests are welcome in GitHub issues.